Chips (including dice, integrated circuits and/or system-on-chips, etc.) form one of the most important hardware foundations of modern information society, chip designers are also eagerly developing better strategy, flow and technology of chip design not only to satisfy basic demands and specifications of customers but also to minimize chip layout area for cost reduction.
Please refer to FIG. 1 illustrating an embodiment of a chip 10. The chip 10 includes a core circuit 14 and an IO interface 12. The core circuit 14 dominates chip functionality and operation, and the IO interface 12 surrounds the core circuit 14 in a ring region. The IO interface 12 includes various signal input and/or output pads generally referred to as signal IO pads which correspond to signal IO pins, as well as IO power pads and IO ground pads which are generally referred to as IO supply pads corresponding to IO supply pins; for example, pads Pio[i−1], Pio[i] and Pio[i+1] shown in FIG. 1 are signal IO pads, a pad Ppwr[j] is an IO power pad, and a pad Pgnd[k] is an IO ground pad.
For the chip 10 to exchange data and signals with external environment such as another chip, active and/or passive element(s) mounted on a same circuit board, each signal IO pad Pio[i] of the IO interface 12 associates with a signal IO cell SION. Via the associated signal IO pad Pio[i], each signal IO cell SIO[i] drives output signal to loading of external environment and/or receives input signal from external environment. The input signal received by a signal IO cell is further transmitted to the core circuit 14, such that the core circuit 14 can work and/or execute functions in response to the input signal. Operation statuses and computation/execution results of the core circuit 14 can also be transmitted to a signal IO cell to be driven as output signal.
Similarly, for the chip 10 to drain required power from external environment, each IO power pad Ppwr[j] associates with an IO power cell IOpwr[j], hence a power voltage Vddext supplied by external environment is distributed as a power voltage VddIO in the chip 10 via a power stripe 16a; also, each IO ground pad Pgnd[k] associates with an IO ground cell IO gnd[k], thus a ground voltage Vssext provided by external environment is distributed as a ground voltage Vss in the chip 10 via a power stripe 16b. The IO power cell IOprw[j] and the IO ground cell IOgnd[k] are generally referred to as IO supply cells.
While purchasing a chip, the application customer of the chips specifies signal IO pins required to be included in the chip, a logic order of the signal IO pins (i.e., a signal IO pin sequence), and timing specifications to be respectively followed by the signal IO pins. According to demands of the signal IO sequence and the timing specifications, the chip designer then performs IO design for the chip, i.e., organizes signal IO cells and IO supply cells for the chip.
The power for the core circuit 14 and the signal IO cells SIO[i] is drained via the IO supply pads. Because each signal IO cell SIO[i] needs to handle signal IO of high voltage and high current, it requires high power; however, high power requirement of the signal IO cells SIO[i] will impact the power voltage VddIO and ground voltage Vss inside the chip 10. For example, when a signal IO cell SIO[i] drives a signal for a switching (transition) from a low level to a high level, the power voltage VddIO suffers a transient drop; when a signal IO cell SIO[i] drives a signal switching from high level to low level, the ground voltage Vss rises temporarily.
As chip needs to serve more functions, it requires more signal IO pads/pins. When many signal IO cells simultaneously drive their output signals to switch (referred to as simultaneous switching output, SSO), impacts to the power voltage VddIO and/or the ground voltage Vss additively accumulate and consequently induce simultaneous switching noise (SSN). For example, at a given moment, assuming a signal IO cell SIO[i1] only needs to steadily and statically maintain a signal of low level; however, if an enough number of other signal IO cells SIO[i2] (i2 not equal to i1) are simultaneously driving switching from high level to low level, signal level of the signal IO cell SIO[i1] will be raised due to the influenced power voltage VddIO and/or ground voltage Vss, and thus fails to be kept at the correct low level; if the signal level of the signal IO cell SIO[i1] is raised above a standard voltage ViL, the IO design violates a ground SSO specification.
Similarly, assuming a signal IO cell SIO[i1] only needs to steadily and statically maintain a signal of high level; however, when an enough number of other signal IO cells SIO[i2] (i2 not equal to i1) are simultaneously driving switching from low level to high level, signal level of the signal IO cell SIO[i1] will be lowered due to the affected power voltage VddIO and/or ground voltage Vss, and then fails to be kept at the correct high level; if the signal level of the signal IO cell SIO[i1] drops below a standard voltage ViH, the IO design violates a power SSO specification. The ground SSO specification and the power SSO specification are generally referred to as an SSO specification.
The power voltage Vddext and ground voltage Vssext supplied by external environment are respectively transmitted to be the power voltage VddIO and ground voltage Vss via a circuit board PCB (e.g., via traces on the circuit board), a chip package PKG (e.g., bonding wires and/or lead frame), associated IO supply pads and power stripes inside the chip. Therefore, when multiple signal IO cells simultaneously drive signal switching and induce SSN, magnitude of the noise relates to equivalent (parasite) circuits of the circuit board, the chip package, the IO supply pads and the power stripes. For example, as inductance of the equivalent circuits becomes greater, resultant impact to the power voltage VddIO and ground voltage Vss is severer, and SSN is stronger. Increasing quantity of the IO supply pads/cells in a chip can effectively reduce inductance of the equivalent circuits; however, an excessively incremented number of IO supply cells/pins will expand overall layout area of the chip and thus increase cost of the chip.
On the other hand, there are different types of signal IO cells; different types of signal IO cells associate with different driving parameters. For example, the driving parameters can include driving strength and slew rate. If a signal IO cell has higher driving strength (and/or slew rate), its signal will benefit from better current amount, quality, characteristics and timing (e.g., waveform, eye diagram, rise time and fall time, etc.), also the signal IO cell can better resist quality variation of circuit board and chip package; however, when such signal IO cell drives signal switching, it causes greater impact to power and ground voltages, and consequently strengthens SSN.
In prior art of IO design technology, each of different types of signal IO cells is assigned with an associated driving factor (DF) according to the SSO specification; the DF of a signal IO cell indicates how many IO supply cells the signal IO cell averagely needs to meet the SSO specification. After selecting associated cell types and quantities for signal IO pins of an IO design, a sum of driving factors (SDF) is evaluated according to quantities of the signal IO cells and their associated driving factors. Based on the SDF, numbers of IO power cells and IO ground cells are determined. For example, assuming a certain chip requires IO signal IO cells of 2 mA (signal IO cells capable of driving output signal by current of 2 mA), 6 signal IO cells of 8 mA and 26 signal IO cells of 24 mA, and the driving factors for the signal IO cells of 2 mA, 8 mA and 24 mA are respectively 0.012, 0.063 and 0.26, then the SDF is computed by 0.012*10+0.063*6+0.26*24=7.258; the SDF is further fine-tuned and rounded, and accordingly concludes that the IO design of the chip needs 8 IO ground cells and 7 IO power cells.
Disadvantages of the aforementioned prior art are discussed as follows. Because the driving factors are fractional, the SDF also includes a fraction portion which is rounded to obtain integer quantities of IO supply cells; hence, IO design of the prior art suffers from over-design, which means that the IO design tends to adopt excessive numbers of IO supply pins, and thus impacts prevalence of chip by increased total pin count, overall layout area and cost of the chip.
Furthermore, the prior art only considers numbers of IO supply cells, while geometric locations of signal IO cells and IO supply cells are left unconsidered. For example, as shown in FIG. 1, the IO power cell IOpwr[j] and IO ground cell IOgnd[k] respectively relay the power voltage VddIO and ground voltage Vss to each signal IO cell SIO[i] via the power stripes 16a and 16b, therefore lengths of the power stripes 16a and 16b (related to distance between signal IO cell and IO power cell, as well as distance between signal IO cell and IO ground cell) and associated parasite effects are factors to affect SSN. However, because the prior art ignores such factors, there is no way to know preferable locations for placing IO supply cells, and it is difficult to achieve better trade-off between SSN suppression and pin count reduction.
In addition, as shown in FIG. 1, each signal IO cell SIO[i] drives an associated external loading LD[i] via the chip package PKG and the circuit board PCB. However, the prior art does not consider parasite effects of chip package and/or circuit board, thus IC designer of prior art tends to adopt signal IO cells of higher driving strength (and/or slew rate), such that timing specifications of signal IO cells are satisfied by expanded driving margin. In other words, due to lack of integrated consideration, IC designer of prior art needs to over-design driving strength. Since signal IO cells of higher driving strength need more IO supply cells to meet SSO specification, reduction of chip pin count is suffered
Moreover, while setting driving factors for different types of signal IO cells, a driving index is first obtained for each type of signal IO cell. The meaning of the driving index can be described as follows: assuming a number N of signal IO cells of a same type are arranged with a single IO ground cell; when the N signal IO cells simultaneously drive signal switching from high level to low level, if another signal IO cell of the same type, which is not driving signal switching, can keep its low-level signal below the standard voltage ViL, then the number N matches a driving index condition. For all numbers N satisfying the driving index condition, the maximum one is taken as the driving index for this type of signal IO cell, and a reciprocal of the driving index is the driving factor associated with this type of signal IO cell. That is, a driving factor only considers signal IO cells of the same type; if the IO design adopts a mixed arrangement including signal IO cells of different types, correctness of driving factor is affected; consequently, the prior art can not assure correctness of whole IO design.